library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity timer is
port(clk,rst:in std_logic;
		demo1:out std_logic_vector(6 downto 0);
		demo2:out std_logic_vector(6 downto 0));
end entity timer;

architecture funs of timer is
component div_frequency is
port(clk:in std_logic;
		rise: out std_logic);
end component div_frequency;
component decoder_7dp is
port(num1:in integer;display1: out std_logic_vector(6 downto 0);
		num2:in integer;display2: out std_logic_vector(6 downto 0));
end component decoder_7dp;
component counter is
port(	clk,rst:in std_logic;
		ge:buffer integer;
		shi:buffer integer);
end component counter;
signal clockout:std_logic;
signal gewei: integer;signal shiwei: integer;
begin
 u1:div_frequency port map(clk,clockout);
 u2:counter port map(clockout,rst,gewei,shiwei);
 u3:decoder_7dp port map(gewei,demo1,shiwei,demo2);
end architecture funs; 